FIG. 1 is a simplified exemplary diagram of a fabricated wafer 100 having a plurality of semiconductor devices 102 occupying regions 104 of the wafer 100. That is, a single semiconductor device 102 can be found in region 106 of the wafer 100. Typically, semiconductor devices 102 in regions 104 are designed as identical units, thereby facilitating mass production of many semiconductor devices.
After fabrication of wafer 100, a variety of testing may be done on the wafer to identify semiconductor devices 102 that are defective. Such testing may be of a “non-contact” nature. For example, incident light may be used to identify manufacturing defects such as thin or thick areas indicating out-of-tolerance regions on the wafer 100.
Or, testing may be of a “contact” nature wherein a probe device (not shown) is coupled to one or more semiconductor devices 102 on wafer 100. Probe contacts are in frictional contact with terminals of a tested semiconductor device 102, referred to as a device under test (DUT), so that a variety of electrical signals are applied to the DUT semiconductor device 102. Output signals from the DUT semiconductor device 102 are then analyzed and compared with expected designed output signals. Defective semiconductor devices 102 are identified when the test output signals do not correspond with the expected designed output signals.
Probe devices have been designed to test individual semiconductor devices 102. Other probe devices are designed to simultaneously test many semiconductor devices. For example, functionality of a processing unit may be verified by applying a test signal pattern and comparing the output of the processing unit with expected designed output signals.
After testing of wafer 100, the individual semiconductor devices 102 are separated from each other, referred to as singulation. The resultant individual semiconductor device 102 residing on a portion of the wafer is referred to as a die 110. Dies 110 passing the wafer testing process are then mounted on a substrate and encapsulated with a protective cover, this assembly is referred to as an integrated circuit (IC) chip 112. It is understood that the IC chip 112 having an encapsulated semiconductor device 102 may have a plurality of discrete subunits 108. For example, an IC chip 112 may include a processing unit and one or more associated memories, or may be a single unit, such as a memory device.
Typically, a “burn-in” process is used to identify IC chips 112 that would otherwise likely fail after a short period of use. Burn-in processes may vary, but generally consist of operating the IC chip 112 while the IC chip 112 is heated to temperatures above expected normal operating conditions. In some burn-in processes, further testing may occur. Accordingly, a variety of electrical signals are applied to the IC chip 112. Output signals are then analyzed and compared with expected designed output signals. Defective IC chips 112 are identified when the test output signals do not correspond with the expected designed output signals.
The IC chips 112 may be further tested after completion of the burn-in process. Such testing may be very sophisticated and complex, providing a thorough test to ensure that all subunits 108 of the IC chip 112 are properly functioning. Those IC chips 112 passing final testing are then attached to a circuit board 114 with other devices 116.
Detected output signals may be processed and saved as test output data during the above-described testing wherein electronic input signals are applied to the semiconductor device 102, to the IC chip 112, or to discrete subunits 108. The saved test data may be archived for later analysis.